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CY7C1021CV26
1-Mbit (64K x 16) Static RAM
Features
* Temperature Range -- Automotive: -40C to 125C * High speed -- tAA = 15 ns * Optimized voltage range: 2.5V-2.7V * Low active power: 360 mW (max.) * Automatic power-down when deselected * Independent control of upper and lower bits * CMOS for optimum speed/power * Packages offered: 44-pin TSOP II and 44-Lead (400-Mil) Molded SOJ * Offered in both lead-free and non lead-free packages an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the end of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW).
Functional Description
The CY7C1021CV26 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has
Logic Block Diagram
DATA IN DRIVERS
A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array 512 X 2048
SENSE AMPS
I/O1-I/O8 I/O9-I/O16
COLUMN DECODER BHE WE CE OE BLE
Selection Guide[1]
CY7C1021CV26-15 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 15 80 10 Unit ns mA mA
Note: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Cypress Semiconductor Corporation Document #: 38-05589 Rev. *A
*
A8 A9 A10 A11 A12 A13 A14 A15
3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised March 7, 2005
CY7C1021CV26
Pin Configuration[2]
TSOP II -Top View
A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
Pin Definitions
Pin Name A0-A15 Pin Number I/O Type Description Address Inputs used to select one of the address locations. 1-5, 18-21, Input 24-27, 42-44 7-10, 13-16, 29-32, 35-38 22, 23, 28 17 6 39, 40 41 Input/Output
I/O1-I/O16
Bidirectional Data I/O lines. Used as input or output lines depending on operation.
NC WE CE BHE, BLE OE
No Connect Input/Control Input/Control Input/Control Input/Control
No Connects. This pin is not connected to the die. Write Enable Input, active LOW. When selected LOW, a Write is conducted. When selected HIGH, a Read is conducted. Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Byte Write Select Inputs, active LOW. BLE controls I/O8-I/O1, BHE controls I/O16-I/O9. Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. Ground for the device. Should be connected to ground of the system. Power Supply inputs to the device.
VSS VCC
12, 34 11, 33
Ground Power Supply
Note: 2. NC pins are not connected on the die.
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CY7C1021CV26
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[3] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] ......................................-0.5V to VCC+0.5V DC Input Voltage[3] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Automotive Ambient Temperature -40C to +125C VCC 2.5V-2.7V
Electrical Characteristics Over the Operating Range
CY7C1021CV26-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 1.0 mA 2.0 -0.3 -3 -3 Min. 2.3 0.4 VCC + 0.3 0.8 +3 +3 -300 80 15 10 Max. Unit V V V V A A mA mA mA mA
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 2.6V Max. 8 8 Unit pF pF
Thermal Resistance[5]
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 44-lead TSOP-II 76.92 15.86 Unit C/W C/W
Notes: 3. VIL (min.) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1021CV26
AC Test Loads and Waveforms[6]
R1 1830 2.6 V OUTPUT R2 30 pF INCLUDING JIG AND SCOPE 1976 Rise Time: 1 V/ns Fall Time: 1 V/ns GND 2.6V 90% 10% ALL INPUT PULSES 90% 10%
(a)
(b)
High-Z characteristics: 2.6V R 317 5 pF R2 351 OUTPUT
(c)
Switching Characteristics Over the Operating Range[7]
CY7C1021CV26-15 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[10] tPD[10] tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD Cycle[11] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End 15 10 10 0 0 10 8 0 ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[8] OE HIGH to CE HIGH to High-Z[8, 9] 3 7 0 15 7 0 7 High-Z[8, 9] CE LOW to Low-Z[8] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z 0 7 3 15 7 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit
Notes: 6. AC characteristics (except High-Z) are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 7. Test conditions assume signal transition time of 2.6 ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.6V. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 10. This parameter is guaranteed by design and is not tested. 11. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
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CY7C1021CV26
Switching Characteristics Over the Operating Range[7] (continued)
CY7C1021CV26-15 Parameter tLZWE tHZWE tBW Description WE HIGH to Low-Z[8] WE LOW to High-Z
[8, 9]
Min. 3
Max. 7
Unit ns ns ns
Byte Enable to End of Write
9
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Notes: 12. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE transition LOW.
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CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes: 15. Data I/O is high-impedance if OE or BHE and/or BLE= VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z High-Z I/O9-I/O16 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z High-Z Power-down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 15 Ordering Code CY7C1021CV26-15ZSE CY7C1021CV26-15VXE CY7C1021CV26-15ZSXE Package Name Z44 V34 Z44 Package Type 44-lead TSOP Type II 44-pin (400-Mil) Molded SOJ (Pb-Free) 44-lead TSOP Type II (Pb-Free) Operating Range Automotive
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CY7C1021CV26
Package Diagrams
44-pin TSOP II Z44
51-85087-*A
44-Lead (400-Mil) Molded SOJ V34
51-85082-*B
All products and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1021CV26
Document History Page
Document Title: CY7C1021CV26 1-Mbit (64K x 16) Static RAM Document Number: 38-05589 REV. ** *A ECN NO. 238454 335861 Issue Date See ECN See ECN Orig. of Change RKF SYT Description of Change New datasheet for Automotive Added Lead-Free Product Information Included the 44-Lead (400-Mil) Molded SOJ V34 Package
Document #: 38-05589 Rev. *A
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